<?xml version="1.0" encoding="utf-8"?>
<FitData version="9.70" sku="LP No Emulation" >
    <BuildSettings label="Build Settings">
        <BuildResults label="Image Build Settings">
            <BuildOutputFilename value="outimage.bin" label="Output Path" />
            <GenIntermediateFiles value="Yes" value_list="No,,Yes" label="Generate Intermediate Files" />
            <BootGrdWrn value="Yes" value_list="No,,Yes" label="Enable Boot Guard warning message at build time" />
            <PTTWrn value="Yes" value_list="No,,Yes" label="Enable Intel (R) Platform Trust Technology warning message at build time" />
            <RegionOrder value="32451" label="Region Order" />
        </BuildResults>
        <PathVars label="Environment Variables">
            <WorkingDir value="." label="$WorkingDir" help_text="Path for environment variable $WorkingDir" />
            <SourceDir value="." label="$SourceDir" help_text="Path for environment variable $SourceDir" />
            <DestDir value="." label="$DestDir" help_text="Path for environment variable $DestDir" />
            <UserVar1 value="." label="$UserVar1" help_text="Path for environment variable $UserVar1" />
            <UserVar2 value="." label="$UserVar2" help_text="Path for environment variable $UserVar2" />
            <UserVar3 value="." label="$UserVar3" help_text="Path for environment variable $UserVar3" />
        </PathVars>
    </BuildSettings>
    <FlashLayout label="Flash Layout">
        <Regions>
            <DescriptorRegion label="Descriptor Region">
                <Length value="0" />
                <OemBinary value="" label="OEM Section Binary" help_text="This loads the OEM Section binary that will be merged into the output image generated by the Intel (R) FIT tool." />
            </DescriptorRegion>
            <GbeRegion label="GbE Region">
                <Length value="0" />
                <InputFile value="" label="GbE Binary File" help_text="This loads the Intel(R) Integrated LAN binary that will be merged into the output image generated by the Intel (R) FIT tool." />
                <Enabled value="Enabled" value_list="Disabled,,Enabled" label="GbE Region Enable" help_text="This option allows the user to enable or disable the Gigabit Ethernet Region." />
            </GbeRegion>
            <MeRegion label="Intel(R) ME Region">
                <Length value="0" />
                <InputFile value="" label="Intel(R) ME Binary File" help_text="This loads the Intel (R) ME binary that will be merged into the output image generated by the Intel(R) FIT tool." />
                <ChipsetInitBinary value="" label="Chipset Initialization Binary" help_text="This loads the Chipset Initialization binary that will be merged into the output image generated by the Intel (R) FIT tool. If specified, this will override the version contained in the Intel (R) ME binary." />
                <IntelTrcHubBinary value="" label="Intel (R) Trace Hub Binary" help_text="This loads the Intel (R) Trace Hub binary that will be merged into the output image generated by the Intel(R) FIT tool." />
            </MeRegion>
            <PdrRegion label="PDR Region">
                <Length value="0" />
                <InputFile value="" label="PDR Binary File" help_text="This loads the Platform Data region binary that will be merged into the output image generated by the Intel (R) FIT tool." />
                <Enabled value="Disabled" value_list="Disabled,,Enabled" label="PDR Region Enable" help_text="This option allows the user to enable or disable the Platform Data Region." />
            </PdrRegion>
            <EcRegion label="EC Region">
                <Length value="0" />
                <InputFile value="" label="EC Binary File" help_text="This loads the Embedded Controller binary used for eSPI that will be merged into the output image generated by the Intel (R) FIT tool." />
                <Enabled value="Disabled" value_list="Disabled,,Enabled" label="EC Region Enable" help_text="This option allows the user to enable or disable the Embedded Controller Data Region." />
            </EcRegion>
            <BiosRegion label="BIOS Region">
                <Length value="0" />
                <InputFile value="" label="BIOS Binary File" help_text="This loads the BIOS binary that will be merged into the output image generated by the Intel (R) FIT tool." />
                <Enabled value="Enabled" value_list="Disabled,,Enabled" label="BIOS Region Enable" help_text="This option allows the user to enable or disable the Bios Region." />
            </BiosRegion>
        </Regions>
    </FlashLayout>
    <FlashSettings label="Flash Settings">
        <FlashComponents label="Flash Components">
            <NumberOfSpiComponents value="2" value_list="0,,1,,2" label="Number of Flash Components" help_text="This setting configures the total number of flash components for the platform.  Note: Choosing a selection of '0' parts will cause the Intel (R) FIT tool to build an output image containing only the Intel (R) ME region." />
            <FlashComponent1Size value="8MB" value_list="512KB,,1MB,,2MB,,4MB,,8MB,,16MB,,32MB,,64MB" label="Flash component 1 Size" help_text="This setting determines the size of Flash component 1 for the platform image." />
            <FlashComponent2Size value="8MB" value_list="512KB,,1MB,,2MB,,4MB,,8MB,,16MB,,32MB,,64MB" label="Flash component 2 Size" help_text="This setting determines the size of Flash component 2 for the platform image.  Note: This setting is only applicable when the Number of Flash Components option is set to '2'." />
            <SpiVoltageSelect value="3.3 Volts" value_list="3.3 Volts,,1.8 Volts" label="SPI Voltage Select" help_text="This strap sets the internal control signal on the pad for either 1.8 or 3.3 V operation.  See Skylake H / LP SPI Programming guide for further details." />
        </FlashComponents>
        <HostCpuBiosMasterAccess label="Host CPU / BIOS Master Access">
            <HostCpuWriteAccess value="0xFFF" value_list="0xFFF,,0x10A,,0x11A" label="Host CPU / BIOS Write Access" help_text="This setting determines write access control for the BIOS region.  For further details on Region Access Control see Skylake H / LP SPI Programming guide." />
            <HostCpuReadAccess value="0xFFF" value_list="0xFFF,,0x10B,,0x11B" label="Host CPU / BIOS Read Access" help_text="This setting determines read access control for the BIOS region.  For further details on Region Access Control see Skylake H / LP SPI Programming guide." />
        </HostCpuBiosMasterAccess>
        <IntelMeMasterAccess label="Intel(R) ME Master Access">
            <MeWriteAccess value="0xFFF" value_list="0xFFF,,0x10C" label="Intel(R) ME Write Access" help_text="This setting determines write access control for the ME region.  For further details on Region Access Control see Skylake H / LP SPI Programming guide." />
            <MeReadAccess value="0xFFF" value_list="0xFFF,,0x10D" label="Intel(R) ME Read Access" help_text="This setting determines read access control for the ME region.  For further details on Region Access Control see Skylake H / LP SPI Programming guide." />
        </IntelMeMasterAccess>
        <GbeMasterAccess label="GbE Master Access">
            <GbeWriteAccess value="0xFFF" value_list="0xFFF,,0x008" label="GbE Write Access" help_text="This setting determines write access control for the Gigabit Ethernet Region.  For further details on Region Access Control see Skylake H / LP SPI Programming guide." />
            <GbeReadAccess value="0xFFF" value_list="0xFFF,,0x009" label="GbE Read Access" help_text="This setting determines read access control for the Gigabit Ethernet Region.  For further details on Region Access Control see Skylake H / LP SPI Programming guide." />
        </GbeMasterAccess>
        <EcMasterAccess label="EC Master Access">
            <EcWriteAccess value="0xFFF" value_list="0xFFF,,0x100" label="Embedded Controller Write Access" help_text="This setting determines write access control for the Embedded Controller region.  For further details on Region Access Control see Skylake H / LP SPI Programming guide." />
            <EcReadAccess value="0xFFF" value_list="0xFFF,,0x100" label="Embedded Controller Read Access" help_text="This setting determines read access control for the Embedded Controller region.  For further details on Region Access Control see Skylake H / LP SPI Programming guide." />
        </EcMasterAccess>
        <FlashConfiguration label="Flash Configuration">
            <SpiDualIoReadEnable value="No" value_list="No,,Yes" label="Dual I/O Read Enabled" help_text="This setting allows customers to enable support for Dual I/O Read capabilities for flash components.  See Skylake H / LP SPI Programming guide for further details." />
            <SpiDualOutReadEnable value="No" value_list="No,,Yes" label="Dual Output Read Enabled" help_text="This setting allows customers to enable support for Dual Output Read capabilities for flash components.  See the Skylake H / LP SPI Programming guide." />
            <FastReadClockFreq value="17MHz" value_list="48MHz,,30MHz,,17MHz" label="Fast Read clock frequency" help_text="This setting allows customers to configure the flash component clock frequency setting for Fast Read.  See Skylake H / LP SPI Programming guide for further details." />
            <FastReadSupport value="No" value_list="No,,Yes" label="Fast Read supported" help_text="This setting allows customers to enable support for Fast Read capabilities for flash components.  See Skylake H / LP SPI Programming guide for further details.  Note: This setting needs to be enabled when using Dual / Quad enabled components." />
            <InvalidInstruction0 value="0x21" label="Invalid Instruction 0" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase.  See Skylake H / LP SPI Programming guide for further details.  Note: This setting should be set to '0' if there are no Invalid instructions." />
            <InvalidInstruction1 value="0x42" label="Invalid Instruction 1" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase.  See Skylake H / LP SPI Programming guide for further details.  Note: This setting should be set to '0' if there are no Invalid instructions." />
            <InvalidInstruction2 value="0x60" label="Invalid Instruction 2" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase.  See Skylake H / LP SPI Programming guide for further details.  Note: This setting should be set to '0' if there are no Invalid instructions." />
            <InvalidInstruction3 value="0xAD" label="Invalid Instruction 3" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase.  See Skylake H / LP SPI Programming guide for further details.  Note: This setting should be set to '0' if there are no Invalid instructions." />
            <InvalidInstruction4 value="0xB7" label="Invalid Instruction 4" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase.  See Skylake H / LP SPI Programming guide for further details.  Note: This setting should be set to '0' if there are no Invalid instructions." />
            <InvalidInstruction5 value="0xB9" label="Invalid Instruction 5" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase.  See Skylake H / LP SPI Programming guide for further details.  Note: This setting should be set to '0' if there are no Invalid instructions." />
            <InvalidInstruction6 value="0xC4" label="Invalid Instruction 6" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase.  See Skylake H / LP SPI Programming guide for further details.  Note: This setting should be set to '0' if there are no Invalid instructions." />
            <InvalidInstruction7 value="0xC7" label="Invalid Instruction 7" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase.  See Skylake H / LP SPI Programming guide for further details.  Note: This setting should be set to '0' if there are no Invalid instructions." />
            <QuadIoReadEnable value="No" value_list="No,,Yes" label="Quad I/O Read Enabled" help_text="This setting allows customers to enable support for Quad I/O Read capabilities for flash components.  See Skylake H / LP SPI Programming guide for further details." />
            <QuadOutReadEnable value="No" value_list="No,,Yes" label="Quad Output Read Enabled" help_text="This setting allows customers to enable support for Quad Output Read capabilities for flash components.  See Skylake H / LP SPI Programming guide for further details." />
            <ReadIdAndReadStatClkFreq value="17MHz" value_list="48MHz,,30MHz,,17MHz" label="Read ID and Read Status clock frequency" help_text="This setting allows customers to configure the flash component clock frequency setting for Read ID and Read Status.  See Skylake H / LP SPI Programming guide for further details." />
            <WriteEraseClockFreq value="17MHz" value_list="48MHz,,30MHz,,17MHz" label="Write and Erase clock frequency" help_text="This setting allows customers to configure the flash component clock frequency setting for Write and Erase.  See Skylake H / LP SPI Programming guide for further details." />
        </FlashConfiguration>
        <VsccTable label="VSCC Table">
            <VsccEntries label="VSCC Entries">
                <VsccEntry label="VSCC Entry">
                    <VsccEntryName value="W25Q128BV" label="Part Name" help_text="This setting allows the OEM input a name designation for each flash component being used.  Note: This is a free form entry field it does not affect actual flash component operation." />
                    <VsccEntryVendorId value="0xEF" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash Component.  See Skylake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId0 value="0x40" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component.  See Skylake H / LP SPI Programming guide for further details." />
                    <VsccEntryDeviceId1 value="0x18" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component.  See Skylake H / LP SPI Programming guide for further details." />
                </VsccEntry>
            </VsccEntries>
        </VsccTable>
        <BiosConfiguration label="Bios Configuration">
            <TopSwapOverride value="64KB" value_list="64KB,,128KB,,256KB,,512KB,,1MB" label="Top Swap Block Size" help_text="This configures the Top Swap Block size for the platform.  For further details see Skylake H / LP Platform Controller Hub EDS." />
        </BiosConfiguration>
    </FlashSettings>
    <IntelMeKernel label="Intel(R) ME Kernel">
        <Processor label="Processor">
            <ProcEmulation value="No Emulation" value_list="No Emulation,,EMULATE Intel (R) vPro (TM) capable Processor,,EMULATE Intel (R) Core (TM) branded Processor,,EMULATE Intel (R) Celeron (R) branded Processor,,EMULATE Intel (R) Pentium (R) branded Processor,,EMULATE Intel (R) Xeon (R) branded Processor,,EMULATE Intel (R) Xeon (R) Manageability capable Processor" label="Processor Emulation" help_text="This setting determines processor type to be emulated on pre-production silicon." />
        </Processor>
        <IntelMeFirmwareUpdate label="Intel (R) ME Firmware Update">
            <FwUpdateOemId value="00000000-0000-0000-0000-000000000000" label="Firmware Update OEM ID" help_text="This setting allows configuration of an OEM unique ID to ensure that customers can only update their platform with images from the OEM of the platform." />
            <HideMEBxFwUpdCtrl value="No" value_list="No,,Yes" label="Hide MEBx Firmware Update Control" help_text="This setting allows customers to hide the Firmware Update option in the MEBx interface." />
            <HmrfpoEnable value="Yes" value_list="No,,Yes" label="Intel(R) ME Region Flash Protection Override" help_text="This setting enables descriptor unlock of the ME Region when the HMRFPO message is sent to firmware prior to BIOS End of POST." />
        </IntelMeFirmwareUpdate>
        <IntelServicesConfiguration label="Intel (R) Services Configuration">
            <OdmIDIntelServices value="0x00000000" label="ODM ID used by Intel(R) Services" help_text="This setting is for entering the ODM ID for Intel(R) Services to identify the ODM Board builder.  Note: This ID is either generated by or registered with Intel(R) Services Web servers." />
            <SysIntIdIntelServices value="0x00000000" label="System Integrator ID used by Intel(R) Services" help_text="This setting is for entering the System Integrator ID for Intel(R) Services to identify the System Integrator.  Note: This ID is either generated by or registered with Intel(R) Services Web servers." />
            <ReservedIdIntelServices value="0x00000000" label="Reserved ID used by Intel(R) Services" help_text="This setting is for entering the Reserved ID for Intel(R) Services currently not used." />
        </IntelServicesConfiguration>
        <ImageIdentification label="Image Identification">
            <OemTag value="0x00000000" label="OEM Tag" help_text="This is a free form 32bit field that allows the OEM to configure their own unique identifier in the firmware image." />
        </ImageIdentification>
        <MctpConfiguration label="MCTP Configuration">
            <MctpStackConfig value="0x920030" label="MCTP Stack Configuration" help_text="Defines the ME's 8-bits MCTP Endpoint IDs for each SMBus physical interface (SMBus, SMLink0 and SMLink1). These values are needed for FW to communicate with MCTP end points. For each of these 3 bytes, a value of 0x00 means not used, and values 0xFF or 0x01 - 0x07 or 0x20 - 0x2F are not allowed." />
            <MctpEspiEnabled value="No" value_list="No,,Yes" />
            <MctpDevicePortEc value="0x00" />
            <MctpDevicePortSio value="0x00" />
            <MctpDevicePortIsh value="0x00" />
            <MctpDevicePortBmc value="0x00" />
        </MctpConfiguration>
        <FirmwareDiagnostics label="Firmware Diagnostics">
            <FwAutoBist value="Disabled" value_list="Disabled,,Enabled" label="Automatic Built in Self Test" help_text="This setting enables the firmware Automatic Built in Self Test which is executed during first platform boot after initial image flashing." />
        </FirmwareDiagnostics>
        <PostManufacturingLock label="Post Manufacturing Lock">
            <NvarPostManLck value="No" value_list="No,,Yes" label="Post Manufacturing NVAR Configuration Enabled" help_text="This setting determines if modifications to Customer configuable NVARs is to be allowed after close of manufacturing." />
        </PostManufacturingLock>
        <Reserved label="Reserved">
            <Reserved value="No" value_list="No,,Yes" />
        </Reserved>
    </IntelMeKernel>
    <IntelAmt label="Intel(R) AMT">
        <IntelAmtConfiguration label="Intel(R) AMT Configuration">
            <AmtSupported value="Yes" value_list="No,,Yes" label="Intel(R) AMT Supported" help_text="This setting allows customers to disable Intel(R) AMT on the platform and force the platform into Standard Manageability mode.  Note: This setting is only applies to Desktop and Workstation platforms." />
            <NetServicesSupported value="Yes" value_list="Yes,,No" label="Intel(R) ME Network Services Supported" help_text="This setting allows customers to enable / disable Intel(R) ME Network Services on the platform.  Note: If this setting is disabled Intel(R) AMT will also be disabled." />
            <MngAppSupported value="Yes" value_list="No,,Yes" label="Manageability Application Supported" help_text="This setting allows customers to permenantly disable Intel(R) AMT and Standard Manageability mode on the platform." />
            <MngAppPowerUpState value="Enabled" value_list="Disabled,,Enabled" label="Manageability Application initial power-up state" help_text="This setting allows customers to determine the power up state for Intel(R) AMT or Standard Manageability.  Note: If this setting is disabled Intel(R) AMT or Standard Manageability can still be re-enabled through the MEBx interface." />
            <AmtIdleTimeout value="0xFFFF" label="Intel(R) AMT Idle Timeout" help_text="This setting configures the idle timeout value before Intel(R) AMT enters into an off state." />
            <AmtWdAutoReset value="No" value_list="No,,Yes" label="Intel(R) AMT Watchdog Automatic Reset Enabled" help_text="This setting allows customers to enable the Intel (R) ME firmware to trigger an automatic platform reset if either the MEI or Agent Presence are in a hung state.  Note: This feature only allows one reset at a time when the watchdog expires.  After this feature has triggered a reset it must be re-armed for re-use via management console." />
        </IntelAmtConfiguration>
        <KvmConfiguration label="KVM Configuration">
            <KvmScreenBlnkEnable value="No" value_list="No,,Yes" label="Firmware KVM Screen Blanking" help_text="This setting enables KVM Screen blanking capabilities in the firmware image.  Note: This feature is dependent on processor level support." />
            <KvmSupported value="Yes" value_list="No,,Yes" label="KVM Redirection Supported" help_text="This setting allows customers to enable / disable the KVM Redirection capabilities of the firmware.  Note: If this setting have been set to disabled it cannot be re-enabled once the descriptor has been locked." />
        </KvmConfiguration>
        <ProvisioningConfiguration label="Provisioning Configuration">
            <EhbcEnable value="No" value_list="No,,Yes" label="Embedded Host Based Configuration Enabled" help_text="This setting allows customers to enable / disable Embedded Host Based Configuration.  Important: EHBC is primarily intended for use in embedded systems as it offers less user privacy/security protection than may be appropriate for business client systems." />
            <PkiDomainSuffix value="" label="PKI Domain Name Suffix" help_text="This setting allows OEMs to pre-configure the Domain Name Suffix used for PKI provisioning in their firmware image.  Note: For normal out-of- box provisioning functionality this setting should be left empty." />
            <OemCustomCert1 label="OEM Customizable Certificate 1">
                <CertActive value="No" value_list="No,,Yes" label="Certificate Enabled" help_text="This setting allows customers to enable PKI provisioning Custom Certificate 1." />
                <CertFriendly value="" label="Certificate Friendly Name" help_text="This setting allows customers to assign a user friendly name for PKI provisioning Custom Certificate 1.  Maximum of 32 characters." />
                <CertStream value="" label="Certificate Stream" help_text="This setting allows customers to input hash stream for PKI provisioning Custom Certificate 1.  If enabled the certificate will be used in addition those already preloaded in base firmware during provisioning.  Note: If the platform is un-configured the Custom Certificate Hash will be deleted." />
            </OemCustomCert1>
            <OemCustomCert2 label="OEM Customizable Certificate 2">
                <CertActive value="No" value_list="No,,Yes" label="Certificate Enabled" help_text="This setting allows customers to enable PKI provisioning Custom Certificate 2." />
                <CertFriendly value="" label="Certificate Friendly Name" help_text="This setting allows customers to assign a user friendly name for PKI provisioning Custom Certificate 2.  Maximum of 32 characters." />
                <CertStream value="" label="Certificate Stream" help_text="This setting allows customers to input hash stream for PKI provisioning custom certificate 2.  If enabled the certificate will be used in addition those already preloaded in base firmware during provisioning.  Note: If the platform is un-configured the Custom Certificate Hash will be deleted." />
            </OemCustomCert2>
            <OemCustomCert3 label="OEM Customizable Certificate 3">
                <CertActive value="No" value_list="No,,Yes" label="Certificate Enabled" help_text="This setting allows customers to enable PKI provisioning Custom Certificate 3." />
                <CertFriendly value="" label="Certificate Friendly Name" help_text="This setting allows customers to assign a user friendly name for PKI provisioning Custom Certificate 3.  Maximum of 32 characters." />
                <CertStream value="" label="Certificate Stream" help_text="This setting allows customers to input hash stream for PKI provisioning Custom Certificate 3.  If enabled the certificate will be used in addition those already preloaded in base firmware during provisioning.  Note: If the platform is un-configured the Custom Certificate Hash will be deleted." />
            </OemCustomCert3>
            <OemDefaultCert1 label="OEM Default Certificate 1">
                <CertActive value="No" value_list="No,,Yes" label="Certificate Enabled" help_text="This setting allows customers to enable PKI provisioning Default certificate 1." />
                <CertFriendly value="" label="Certificate Friendly Name" help_text="This setting allows customers to assign a user friendly name for PKI provisioning Default Certificate 1.  Maximum of 32 characters." />
                <CertStream value="" label="Certificate Stream" help_text="This setting allows customers to input hash stream for PKI provisioning custom certificate 1.  Note: Default Certificates if enabled will be used in addition those already preloaded in firmware during provisioning.  Unlike Customizable Certificates the Default Certificates are not deleted when the platform is un-provisioned." />
            </OemDefaultCert1>
            <OemDefaultCert2 label="OEM Default Certificate 2">
                <CertActive value="No" value_list="No,,Yes" label="Certificate Enabled" help_text="This setting allows customers to enable PKI provisioning Default certificate 2." />
                <CertFriendly value="" label="Certificate Friendly Name" help_text="This setting allows customers to assign a user friendly name for PKI provisioning Default Certificate 2.  Maximum of 32 characters." />
                <CertStream value="" label="Certificate Stream" help_text="This setting allows customers to input hash stream for PKI provisioning custom certificate 2.  Note: Default Certificates if enabled will be used in addition those already preloaded in firmware during provisioning.  Unlike Customizable Certificates the Default Certificates are not deleted when the platform is un-provisioned." />
            </OemDefaultCert2>
            <OemDefaultCert3 label="OEM Default Certificate 3">
                <CertActive value="No" value_list="No,,Yes" label="Certificate Enabled" help_text="This setting allows customers to enable PKI provisioning Default certificate 3." />
                <CertFriendly value="" label="Certificate Friendly Name" help_text="This setting allows customers to assign a user friendly name for PKI provisioning Default Certificate 3.  Maximum of 32 characters." />
                <CertStream value="" label="Certificate Stream" help_text="This setting allows customers to input hash stream for PKI provisioning custom certificate 3.  Note: Default Certificates if enabled will be used in addition those already preloaded in firmware during provisioning.  Unlike Customizable Certificates the Default Certificates are not deleted when the platform is un-provisioned." />
            </OemDefaultCert3>
            <OemDefaultCert4 label="OEM Default Certificate 4">
                <CertActive value="No" value_list="No,,Yes" label="Certificate Enabled" help_text="This setting allows customers to enable PKI provisioning Default certificate 4." />
                <CertFriendly value="" label="Certificate Friendly Name" help_text="This setting allows customers to assign a user friendly name for PKI provisioning Default Certificate 4.  Maximum of 32 characters." />
                <CertStream value="" label="Certificate Stream" help_text="This setting allows customers to input hash stream for PKI provisioning custom certificate 4.  Note: Default Certificates if enabled will be used in addition those already preloaded in firmware during provisioning.  Unlike Customizable Certificates the Default Certificates are not deleted when the platform is un-provisioned." />
            </OemDefaultCert4>
            <OemDefaultCert5 label="OEM Default Certificate 5">
                <CertActive value="No" value_list="No,,Yes" label="Certificate Enabled" help_text="This setting allows customers to enable PKI provisioning Default certificate 5." />
                <CertFriendly value="" label="Certificate Friendly Name" help_text="This setting allows customers to assign a user friendly name for PKI provisioning Default Certificate 5.  Maximum of 32 characters." />
                <CertStream value="" label="Certificate Stream" help_text="This setting allows customers to input hash stream for PKI provisioning custom certificate 5.  Note: Default Certificates if enabled will be used in addition those already preloaded in firmware during provisioning.  Unlike Customizable Certificates the Default Certificates are not deleted when the platform is un-provisioned." />
            </OemDefaultCert5>
        </ProvisioningConfiguration>
        <RedirectionConfiguration label="Redirection Configuration">
            <RedirectionLanguage value="English" label="Redirection Localized Language" help_text="This setting allows customers to configure which localized language will be used initially by firmware for user consent output information (Examples: may be displayed before SOL / KVM session starts)." />
            <RedirectionPrivSecLevel value="Default" value_list="Default,,Enhanced,,Extreme" label="Redirection Privacy / Security Level" help_text="This setting allows customers to configure the Privacy and Security level for redirection operations.  Default enables all redirection ports (User consent is configurable).  Enhanced enables all redirection ports (User consent is required and cannot be disabled).  Extreme disables all redirection capabilities." />
        </RedirectionConfiguration>
        <TlsConfiguration label="TLS Configuration">
            <TlsSupported value="Yes" value_list="No,,Yes" label="Transport Layer Security Supported" help_text="This setting allows customers to enable / disable firmware Transport Layer Security support.  Note: If this is disabled TLS will be permanently disabled in the firmware image." />
        </TlsConfiguration>
    </IntelAmt>
    <PlatformProtection label="Platform Protection">
        <ContentProtection label="Content Protection">
            <PavpSupported value="Yes" value_list="No,,Yes" label="PAVP Supported" help_text="This setting determines if the Protected Audio Video Path (PAVP) feature will be permanently disabled in the firmware image." />
            <Lspcon4kdisp value="None" value_list="None,,PortB,,PortC,,PortD" label="LSPCON Internal Display Port 1 - LSPCON / 4K" help_text="This setting determines which port for LSPCON will be connected to the HDCP 2.2 bridge adapter Display 1." />
            <Hdcp5kedisp1 value="PortA" value_list="None,,PortA,,PortB,,PortC,,PortD" label="HDCP Internal Display Port 1 - 5K" help_text="This setting determines which port is connected for 5K output on Internal Display 1.  Note: Both Display 1 &amp; 2 need to be configured for proper operation." />
            <Hdcp5kedisp2 value="None" value_list="None,,PortA,,PortB,,PortC,,PortD" label="HDCP Internal Display Port 2 - 5K" help_text="This setting determines which port is connected for 5K output on Internal Display 2.  Note: Both Display 1 &amp; 2 need to be configured for proper operation." />
        </ContentProtection>
        <GraphicsuController label="Graphics uController">
            <GucHash value="00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00" label="GuC Encryption Key" help_text="This option is for entering the raw hash 256 bit string for the Graphics uController." />
        </GraphicsuController>
        <KeyConfiguration label="Hash Key Configuration for Bootguard / ISH">
            <OemPublicKeyHash value="00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00" label="OEM Public Key Hash" help_text="This option is for entering the raw hash string for Boot Guard or ISH.  This 256-bit field represents the SHA-256 hash of the OEM public key corresponding to the private key used to sign the BIOS-SM for Bootguard or ISH firmware." />
        </KeyConfiguration>
        <BootGuardConfiguration label="Boot Guard Configuration">
            <BtGuardKeyManifestId value="0x0" label="Key Manifest ID" help_text="This option is for entering the hash of another public key, used by the ACM to verify the Boot Policy Manifest." />
            <BtGuardProfileConfig value="Boot Guard Profile 0 - No_FVME" value_list="Boot Guard Profile 0 - No_FVME,,Boot Guard Profile 1 - VE,,Boot Guard Profile 2 - VME,,Boot Guard Profile 3 - VM,,Boot Guard Profile 4 - FVE,,Boot Guard Profile 5 - FVME" label="Boot Guard Profile Configuration" help_text="This option configures the which Boot Guard Policy Profile will be used." />
            <BtGuardCpuDebugEnable value="Enabled" value_list="Enabled,,Disabled" label="CPU Debugging" help_text="When set to Enabled the CPU debugging capability probe mode is enabled.  When this field is set to Disabled it indicates CPU debugging capability probe mode is disabled and locked." />
            <BtGuardBspInitEnable value="Enabled" value_list="Enabled,,Disabled" label="BSP Initialization" help_text="This setting determines BSP behavior when it receives an INIT signal.  When set to 'Enabled', when BSP receives an INIT, BSP will signal an error to the BSS register and enter unrecoverable shutdown." />
        </BootGuardConfiguration>
        <IntelPttConfiguration label="Intel (R) PTT Configuration">
            <PttPwrUpState value="Enabled" value_list="Disabled,,Enabled" label="Intel(R) PTT initial power-up state" help_text="This setting determines if Intel(R) PTT is enabled on platform power-up." />
            <PttSupported value="Yes" value_list="Yes,,No" label="Intel(R) PTT Supported" help_text="This setting permanently disables Intel(R) PTT in the firmware image." />
            <PttSupportedHw value="Yes" value_list="No,,Yes" label="Intel(R) PTT Supported [FPF]" help_text="This setting will permanently disable Intel(R) PTT through platform FPFs.  Caution: Using this option will permanently disable Intel(R) PTT on the platform hardware." />
            <PttRtcClearDetect value="Enabled" value_list="Enabled,,Disabled" label="Intel(R) PTT RTC Clear Detection" help_text="This setting determines how the Intel(R) PTT will behave when RTC (CMOS) clear is triggered on the platform.  When Disabled Intel(R) PTT will bypass normal RTC clear behavior. Note: For designs where there is no Physical Coin Cell Battery, for backing up data stored in the RTC well, this setting should be set to 'Disabled'." />
        </IntelPttConfiguration>
        <TpmOverSpiBusConfiguration label="TPM Over SPI Bus Configuration">
            <SpiOverTpmClkFreq value="17MHz" value_list="17MHz,,30MHz,,48MHz" label="TPM Clock Frequency" help_text="This setting determines the clock frequency setting to be used for the TPM over SPI bus." />
            <SpiOverTpmBusEnable value="No" value_list="No,,Yes" label="TPM Over SPI Bus Enabled" help_text="This setting determines if TPM over SPI bus is enabled on the platform." />
        </TpmOverSpiBusConfiguration>
    </PlatformProtection>
    <Icc label="Integrated Clock Controller">
        <IccPolicies label="Integrated Clock Controller Policies">
            <RegisterLockPolicy value="0:Default" value_list="0:Default,,1:All Locked,,2:All Unlocked" label="Register Lock Policy" help_text="Policy applied to ICC Registers at EOP." />
            <BootProfile value="Profile 0" value_list="Profile 0" label="Boot Profile" help_text="Profile applied during each boot." />
            <FailsafeBootProfile value="Profile 0" value_list="Profile 0" label="Failsafe Boot Profile" help_text="Boot profile used when system instability is detected." />
            <ProfileChangeable value="true" value_list="true,,false" label="Profile Changeable" help_text="True = Allows user to change boot profile via BIOS menu or 3rd party application False = Prevents user from changing boot profile via BIOS or 3rd party application.  Note: When false, Failsafe Boot Profile must be the same as Boot Profile." />
            <Profiles>
                <Profile label="Profile">
                    <ProfileName value="Profile 0" label="Profile Name" help_text="Editable text string stored with the profile for easy identification." />
                    <ProfileType value="Standard" value_list="Standard,,Adaptive" label="Profile Type" help_text="Specifies the profile template used when creating the profile.  Intel (R) ME image has to be loaded to enable other ICC profile settings." />
                </Profile>
            </Profiles>
        </IccPolicies>
    </Icc>
    <NetworkingConnectivity label="Networking &amp; Connectivity">
        <WiredLanConfiguration label="Wired LAN Configuration">
            <GbeMacSmbAddrs value="0x70" label="GbE MAC SMBus Address" help_text="This setting configures Intel(R) Integrated Wired LAN MAC SMBus address to accept SMBus cycles from the PHY.  Note: Recommended setting is 70h." />
            <GbeMacSmbAddrsEn value="Yes" value_list="No,,Yes" label="GbE MAC SMBus Address Enabled" help_text="This enables the Intel(R) Integrated Wired LAN MAC SMBus address.  Note: This setting must be enabled if using Intel(R) Integrated LAN." />
            <GbePhyPcieEnable value="Yes" value_list="No,,Yes" label="Intel(R) PHY over PCIe Enabled" help_text="This setting allows customers to enable / disable Intel(R) Integrated LAN operation over the PCIe Port selected by the GbE PCIe Port Select option." />
            <GbePCIePortSelect value="PORT5" value_list="PORT3,,PORT4,,PORT5,,PORT9,,PORT10" label="GbE PCIe Port Select" help_text="This setting allows customers to configure the PCIe Port that will Intel(R) Integrated LAN will operate on." />
            <GbePHYSmbAddrs value="0x64" label="GbE PHY SMBus Address" help_text="This setting configures Intel(R) Integrated Wired LAN SMBus address to accept SMBus cycles from the MAC.  Note: Recommended setting is 64h." />
            <MELanPowerWell value="SLP_LAN#" value_list="Core Well,,SUS Well,,ME Well,,SLP_LAN#" label="LAN Power Well" help_text="This setting allows the customer to configure the powerwell that will be used by Intel(R) Integrated LAN.  Note: Recommended setting is SLP_LAN#." />
            <LanPhyPwrCtrlGpd11Config value="LANPHYPC" value_list="GPD11,,LANPHYPC" label="LAN PHY Power Control GPD11 Signal Configuration" help_text="This setting allows the user to assign the LAN PHY Power Control signal to GbE or as GPD11.  Note: If using Intel(R) Integrated LAN this setting should be set to 'LANPHYPC'." />
            <LanPhyPwrUpTime value="100ms" value_list="100ms,,50ms" label="LAN PHY Power Up Time" help_text="This bit determines how long the delay for LAN PHY to power up after de-assertion of SLP_LAN#." />
            <LanEnable value="Enabled" value_list="Enabled,,Disabled" label="Intel(R) Integrated Wired LAN Enable" help_text="This setting allows customers to enable / disable Intel(R) Integrated LAN operation over the PCIe Port selected by the GbE PCIe Port Select option." />
            <PhyConnected value="PHY on SMLink0" value_list="No PHY Connected,,PHY on SMBus,,PHY on SMLink0,,PHY on SMLink1" label="PHY Connection" help_text="This selects which SMBus network is used to connect GbE Legacy PHY to MAC/PCH." />
        </WiredLanConfiguration>
        <WirelessLanConfiguration label="Wireless LAN Configuration">
            <MeClinkEnable value="Yes" value_list="No,,Yes" label="Intel (R) ME CLINK Signal Enabled" help_text="This setting allows customers to enable / disable the Wireless LAN CLINK signal through Intel (R) ME firmware.  Note: For using Intel(R) vPro Wireless solutions this should be set to 'Yes'." />
            <WlanUcode value="0x24F3 SNOWFIELD" label="WLAN Microcode" help_text="This setting allows OEMs to configure which Intel(R) Wireless LAN card microcode to load into the firmware image." />
            <MEWlanPowerWell value="SLP_WLAN#" value_list="Disabled,,Core Well || SLP_S3#,,Primary Well || SLP_SUS#,,ME Well || SLP_A#,,SLP_WLAN#" label="WLAN Power Well" help_text="This setting allows the customer to configure the powerwell that will be used by Intel(R) Wireless LAN.  Note: Recommended setting is SLP_WLAN#." />
            <SlpWlanGpd9Config value="SLP_WLAN#" value_list="SLP_WLAN#,,GPD9" label="SLP_WLAN# / GPD9 Signal Configuration" help_text="This setting allows the user to assign the WLAN Power Control signal to WLAN or as GPD9.  Note: If using Intel(R) Wireless LAN this setting should be set to 'SLP_WLAN#'." />
        </WirelessLanConfiguration>
        <IntelNfcConfiguration label="Intel (R) NFC Configuration">
            <NfcEnable value="No" value_list="No,,Yes" label="Enable Near Field Communication" />
            <NfcSmbusAddress value="0x28-NXP" value_list="0x28-NXP,,0x29-NXP,,0x2A-NXP,,0x2B-NXP" label="NFC SMBus Address" />
        </IntelNfcConfiguration>
    </NetworkingConnectivity>
    <FlexIo label="Flex I/O">
        <IntelRstForPcieConfiguration label="Intel(R) RST for PCIe Configuration">
            <RstPCIe1C2Select value="x2" value_list="x2,,x4" label="Intel(R) RST for PCIe-C2 Select x2 or x4" help_text="This is used to configure NAND Cycle routers for the Intel(R) RST for PCIe interface as either x2 or x4 lane operation on PCIe Controller 2 [LP] or PCIe Controller 4 [S / H].  Note: This setting must match port configuration settings of Intel (R) RST for PCIe Controller 2 and PCIe Controller 2 [LP] or PCIe Controller 4 [S / H]." />
            <RstPCIe1C3Select value="x2" value_list="x2,,x4" label="Intel(R) RST for PCIe-C3 Select x2 or x4" help_text="This is used to configure NAND Cycle routers for the Intel(R) RST for PCIe interface as either x2 or x4 lane operation on PCIe Controller 3 [LP] or PCIe Controller 5 [S / H].  Note: This setting must match port configuration settings of Intel (R) RST for PCIe Controller 3 and PCIe Controller 3 [LP] or PCIe Controller 5 [S / H]." />
            <RstPCIeController2 value="2x2" value_list="2x2,,1x4" label="Intel(R) RST for PCIe Controller 2" help_text="This is used to configure PCIe Controller 2 for Intel(R) RST for PCIe interface as either x2 or x4 lane operation on PCIe Controller 2 [LP] or PCIe Controller 4 [S / H].  Note: This setting must match port configuration settings of Intel(R) RST for PCIe-C2 Select x2 or x4 and PCIe Controller 2 [LP] or PCIe Controller 4 [S / H]." />
            <RstPCIeController3 value="2x2" value_list="2x2,,1x4" label="Intel(R) RST for PCIe Controller 3" help_text="This is used to configure PCIe Controller 3 for Intel(R) RST for PCIe interface as either x2 or x4 lane operation on PCIe Controller 3 [LP] or PCIe Controller 5 [S / H].  Note: This setting must match port configuration settings of Intel(R) RST for PCIe-C3 Select x2 or x4 and PCIe Controller 3 [LP] or PCIe Controller 5 [S / H]." />
            <PCIeCtrl2Port1SrisEnable value="No" value_list="No,,Yes" label="PCIe Controller 2 Port 1 SRIS Enabled" help_text="This is used to configure SRIS Port 1 for Intel(R) RST for PCIe on PCIe Controller 2.  Note: Configuration of this setting is only required if the NVM device will be connected external SATA Express cable." />
            <PCIeCtrl2Port2SrisEnable value="No" value_list="No,,Yes" label="PCIe Controller 2 Port 2 SRIS Enabled" help_text="This is used to configure SRIS Port 2 for Intel(R) RST for PCIe on PCIe Controller 2.  Note: Configuration of this setting is only required if the NVM device will be connected external SATA Express cable." />
            <PCIeCtrl2Port3SrisEnable value="No" value_list="No,,Yes" label="PCIe Controller 2 Port 3 SRIS Enabled" help_text="This is used to configure SRIS Port 3 for Intel(R) RST for PCIe on PCIe Controller 2.  Note: Configuration of this setting is only required if the NVM device will be connected external SATA Express cable." />
            <PCIeCtrl2Port4SrisEnable value="No" value_list="No,,Yes" label="PCIe Controller 2 Port 4 SRIS Enabled" help_text="This is used to configure SRIS Port 4 for Intel(R) RST for PCIe on PCIe Controller 2.  Note: Configuration of this setting is only required if the NVM device will be connected external SATA Express cable." />
            <PCIeCtrl3Port1SrisEnable value="No" value_list="No,,Yes" label="PCIe Controller 3 Port 1 SRIS Enabled" help_text="This is used to configure SRIS Port 1 for Intel(R) RST for PCIe on PCIe Controller 3.  Note: Configuration of this setting is only required if the NVM device will be connected external SATA Express cable." />
            <PCIeCtrl3Port2SrisEnable value="No" value_list="No,,Yes" label="PCIe Controller 3 Port 2 SRIS Enabled" help_text="This is used to configure SRIS Port 2 for Intel(R) RST for PCIe on PCIe Controller 3.  Note: Configuration of this setting is only required if the NVM device will be connected external SATA Express cable." />
            <PCIeCtrl3Port3SrisEnable value="No" value_list="No,,Yes" label="PCIe Controller 3 Port 3 SRIS Enabled" help_text="This is used to configure SRIS Port 3 for Intel(R) RST for PCIe on PCIe Controller 3.  Note: Configuration of this setting is only required if the NVM device will be connected external SATA Express cable." />
            <PCIeCtrl3Port4SrisEnable value="No" value_list="No,,Yes" label="PCIe Controller 3 Port 4 SRIS Enabled" help_text="This is used to configure SRIS Port 4 for Intel(R) RST for PCIe on PCIe Controller 3.  Note: Configuration of this setting is only required if the NVM device will be connected external SATA Express cable." />
        </IntelRstForPcieConfiguration>
        <PcieLaneReversalConfiguration label="PCIe Lane Reversal Configuration">
            <PCIeCtrl1LnReversal value="No" value_list="No,,Yes" label="PCIe Controller 1 Lane Reversal Enabled" help_text="This setting allows the PCIe lanes on Controller 1 to be reversed.  For further details see Skylake H / LP Platform Controller Hub EDS." />
            <PCIeCtrl2LnReversal value="No" value_list="No,,Yes" label="PCIe Controller 2 Lane Reversal Enabled" help_text="This setting allows the PCIe lanes on Controller 2 to be reversed.  For further details see Skylake H / LP Platform Controller Hub EDS." />
            <PCIeCtrl3LnReversal value="No" value_list="No,,Yes" label="PCIe Controller 3 Lane Reversal Enabled" help_text="This setting allows the PCIe lanes on Controller 3 to be reversed.  For further details see Skylake H / LP Platform Controller Hub EDS." />
        </PcieLaneReversalConfiguration>
        <PciePortConfiguration label="PCIe Port Configuration">
            <PCIeController1Config value="1x4" value_list="4x1,,1x2, 2x1,,2x2,,1x4" label="PCIe Controller 1 (Port 1-4)" help_text="This setting controls PCIe Port configurations for PCIe Controller 1.  For further details see Skylake H / LP Platform Controller Hub EDS." />
            <PCIeController2Config value="4x1" value_list="4x1,,1x2, 2x1,,2x2,,1x4" label="PCIe Controller 2 (Port 5-8)" help_text="This setting controls PCIe Port configurations for PCIe Controller 2.  For further details see Skylake H / LP Platform Controller Hub EDS." />
            <PCIeController3Config value="4x1" value_list="4x1,,1x2, 2x1,,2x2,,1x4" label="PCIe Controller 3 (Port 9-12)" help_text="This setting controls PCIe Port configurations for PCIe Controller 3.  For further details see Skylake H / LP Platform Controller Hub EDS.  Note: For Skylake-LP Base U and Premium Y PCIe Controller 3 has only Port 9-10 and is limited to 1x2, 2x1 port configuration only.  For these platforms use only the 1x2, 2x1 and 2x2 settings for port configurations." />
        </PciePortConfiguration>
        <SataPcieComboPortConfiguration label="SATA / PCIe Combo Port Configuration">
            <SataPCIeComboPort0 value="SATA" value_list="SATA,,PCIe (or GbE),,GPIO" label="SATA / PCIe Combo Port 0" help_text="This setting configures the PCIe port to operate as either PCIe Port 7 or SATA Port 0.  For further details on Flex I/O see Skylake H / LP Platform Controller Hub EDS." />
            <SataPCIeComboPort1 value="GPIO" value_list="SATA,,PCIe (or GbE),,GPIO" label="SATA / PCIe Combo Port 1" help_text="This setting configures the PCIe port to operate as either PCIe Port 8 or SATA Port 1.  For further details on Flex I/O see Skylake H / LP Platform Controller Hub EDS." />
            <SataPCIeComboPort2 value="PCIe (or GbE)" value_list="SATA,,PCIe (or GbE),,GPIO" label="SATA / PCIe Combo Port 2" help_text="This setting configures the PCIe port to operate as either PCIe Port 11 or SATA Port 1.  For further details on Flex I/O see Skylake H / LP Platform Controller Hub EDS.  Note: This setting is only valid for For Skylake Premium U." />
            <SataPCIeComboPort3 value="PCIe (or GbE)" value_list="SATA,,PCIe (or GbE),,GPIO" label="SATA / PCIe Combo Port 3" help_text="This setting configures the PCIe port to operate as either PCIe Port 12 or SATA Port 2.  For further details on Flex I/O see Skylake H / LP Platform Controller Hub EDS.  Note: This Combo Port only applies to ULT based MCPs.  Note: This setting is only valid for For Skylake Premium U." />
        </SataPcieComboPortConfiguration>
        <SataPcieComboPortSelectPolarity label="SATA / PCIe Combo Port Select Polarity">
            <SataPCIePolSelComboPort0 value="0 = PCIe" value_list="0 = PCIe,,0 = SATA" label="Polarity Select SATA / PCIe Combo Port 0" help_text="This setting is used to determine the native mode configuration for SATA / PCIe Combo Port 0.  For further details on Flex I/O see Skylake H / LP Platform Controller Hub EDS." />
            <SataPCIePolSelComboPort1 value="0 = PCIe" value_list="0 = PCIe,,0 = SATA" label="Polarity Select SATA / PCIe Combo Port 1" help_text="This setting is used to determine the native mode configuration for SATA / PCIe Combo Port 1.  For further details on Flex I/O see Skylake H / LP Platform Controller Hub EDS." />
            <SataPCIePolSelComboPort2 value="0 = PCIe" value_list="0 = PCIe,,0 = SATA" label="Polarity Select SATA / PCIe Combo Port 2" help_text="This setting is used to determine the native mode configuration for SATA / PCIe Combo Port 2.  For further details on Flex I/O see Skylake H / LP Platform Controller Hub EDS." />
            <SataPCIePolSelComboPort3 value="0 = PCIe" value_list="0 = PCIe,,0 = SATA" label="Polarity Select SATA / PCIe Combo Port 3" help_text="This setting is used to determine the native mode configuration for SATA / PCIe Combo Port 3.  For further details on Flex I/O see Skylake H / LP Platform Controller Hub EDS." />
        </SataPcieComboPortSelectPolarity>
        <Usb3PortConfiguration label="USB3 Port Configuration">
            <USB3PCIeComboPort0 value="PCIe (or GbE)" value_list="USB3,,PCIe (or GbE)" label="USB3 / PCIe Combo Port 0" help_text="This setting configures the PCIe port to operate as either PCIe Port 1 or USB3 Port 5.  For further details on Flex I/O see Skylake H / LP Platform Controller Hub EDS." />
            <USB3PCIeComboPort1 value="PCIe (or GbE)" value_list="USB3,,PCIe (or GbE)" label="USB3 / PCIe Combo Port 1" help_text="This setting configures the PCIe port to operate as either PCIe Port 2 or USB3 Port 6.  For further details on Flex I/O see Skylake H / LP Platform Controller Hub EDS." />
            <USB3SSICComboPort1 value="USB3" value_list="USB3,,SSIC" label="USB3 / SSIC Combo Port 1" help_text="This setting configures USB3 Port 2 to operate as either USB3 or SSIC.  For further details on Flex I/O see Skylake H / LP Platform Controller Hub EDS." />
        </Usb3PortConfiguration>
        <XhciPortConfiguration label="XHCI Port Configuration">
            <XHCIPort1Ownership value="XHCI" value_list="XHCI,,Non-XHCI" label="XHCI Port 1 Ownership" help_text="This setting configures USB3 Port 1 to operate as either XHCI or Non-XHCI.  For further details on Flex I/O see Skylake H / LP Platform Controller Hub EDS." />
            <XHCIPort2Ownership value="XHCI" value_list="XHCI,,Non-XHCI" label="XHCI Port 2 Ownership" help_text="This setting configures USB3 Port 2 to operate as either XHCI or Non-XHCI.  For further details on Flex I/O see Skylake H / LP Platform Controller Hub EDS." />
            <XHCIPort3Ownership value="XHCI" value_list="XHCI,,Non-XHCI" label="XHCI Port 3 Ownership" help_text="This setting configures USB3 Port 3 to operate as either XHCI or Non-XHCI.  For further details on Flex I/O see Skylake H / LP Platform Controller Hub EDS." />
            <XHCIPort4Ownership value="XHCI" value_list="XHCI,,Non-XHCI" label="XHCI Port 4 Ownership" help_text="This setting configures USB3 Port 4 to operate as either XHCI or Non-XHCI.  For further details on Flex I/O see Skylake H / LP Platform Controller Hub EDS." />
            <XHCIPort5Ownership value="Non-XHCI" value_list="XHCI,,Non-XHCI" label="XHCI Port 5 Ownership" help_text="This setting configures USB3 Port 5 to operate as either XHCI or Non-XHCI.  For further details on Flex I/O see Skylake H / LP Platform Controller Hub EDS." />
            <XHCIPort6Ownership value="Non-XHCI" value_list="XHCI,,Non-XHCI" label="XHCI Port 6 Ownership" help_text="This setting configures USB3 Port 6 to operate as either XHCI or Non-XHCI.  For further details on Flex I/O see Skylake H / LP Platform Controller Hub EDS." />
        </XhciPortConfiguration>
    </FlexIo>
    <InternalPchBuses label="Internal PCH Buses">
        <OpiConfiguration label="OPI Configuration">
            <OpiLinkSpeed value="GT2" value_list="GT2,,GT4" label="OPI Link Speed" help_text="This setting configures the OPI Link Speed.  For further details see Skylake PCH EDS." />
            <OpiLinkWidth value="8 Lanes" value_list="1 Lane,,2 Lanes,,4 Lanes,,8 Lanes" label="OPI Link Width" help_text="This setting configures the OPI Link Width.  For further details see Skylake PCH EDS." />
            <OpiLinkVoltage value="0.95 Volts" value_list="0.95 Volts,,0.85 Volts" label="OPI Link Voltage" help_text="This setting configures the OPI Link Voltage.  For further details see Skylake PCH EDS." />
        </OpiConfiguration>
        <DmiConfiguration label="DMI Configuration">
            <DmiLaneReversal value="No" value_list="No,,Yes" label="DMI Lane Reversal" help_text="This setting allows the DMI Lane signals to be reversed.  For further details see Skylake H / LP Platform Controller Hub EDS." />
            <DmiPciPortStagger value="Yes" value_list="No,,Yes" label="DMI Port Staggering" help_text="This setting configures DMI for Port Staggering.  For further details see Skylake H / LP Platform Controller Hub EDS." />
        </DmiConfiguration>
        <EspiConfiguration label="eSPI Configuration">
            <EspiEcBootEnable value="Yes" value_list="Yes,,No" label="eSPI / EC Boot Enabled" />
            <EspiEcBusfreq value="60MHz" value_list="20MHz,,24MHz,,30MHz,,48MHz,,60MHz" label="eSPI / EC Bus Frequency" />
            <EspiEcCrcCheckEnable value="Yes" value_list="Yes,,No" label="eSPI / EC CRC Check Enabled" />
            <EspiEcMaxOutReqMstrFlCh value="2" value_list="2,,1" label="eSPI / EC Max Outstanding Requests for Master Attached Flash Channel" />
            <EspiEcMaxPldSizeMstrFlCh value="64 bytes" value_list="64 bytes,,128 bytes,,256 bytes,,512 bytes,,1024 bytes,,2048 bytes,,4096 bytes" label="eSPI / EC Max Read Request Payload size for Master Attached Flash Channel" />
            <EspiEcMaxPldSizeOOBCh value="64 bytes" value_list="64 bytes,,128 bytes,,256 bytes,,512 bytes,,1024 bytes,,2048 bytes,,4096 bytes" label="eSPI / EC Max Read Request Payload size for OOB Channel" />
            <EspiEcMaxPldSizePeriphCh value="64 bytes" value_list="64 bytes,,128 bytes,,256 bytes,,512 bytes,,1024 bytes,,2048 bytes,,4096 bytes" label="eSPI / EC Max Read Request Payload size for Peripheral Channel" />
            <EspiEcMaxVirtualWireCh value="8" value_list="8,,4,,2,,1" label="eSPI / EC Max Virtual Wire Channels" />
            <EspiEcMaxIoMode value="Single, Dual and Quad" value_list="Single,,Single and Dual,,Single and Quad,,Single, Dual and Quad" label="eSPI / EC Maximum I/O Mode" />
            <EspiEcOobChEnable value="Yes" value_list="Yes,,No" label="eSPI / EC OOB Channel Enabled" />
            <EspiEcPeriphChEnable value="Yes" value_list="Yes,,No" label="eSPI / EC Peripheral Channel Enabled" />
        </EspiConfiguration>
        <PchTimerConfiguration label="PCH Timer Configuration">
            <ApwrokTiming value="2 ms" value_list="2 ms,,4 ms,,8 ms,,16 ms" label="APWROK Timing" help_text="This soft strap determines the time between the SLP_A# pin de-asserting and the APWROK timer expiration.  For further details see Skylake H / LP Platform Controller Hub EDS." />
            <t573TimingConfig value="1 ms" value_list="1 ms,,5 ms,,50 ms,,100 ms" label="PCH clock output stable to PROCPWRGD high (tPCH45)" help_text="This setting configures the minimum timing from XCK_PLL locked to CPUPWRGD high.  For further details see Skylake H / LP Platform Controller Hub EDS." />
            <t36TimerEnable value="Disabled" value_list="Disabled,,Enabled" label="PCIe Power Stable Timer (tPCH33)" help_text="This setting configures the enables / disables the tPCH33 timer.  When enabled PCH will count 99ms from PWROK assertion before PLTRST# is de-asserted.  Note: The recommended setting is 'Disabled'." />
            <t1001TimingConfig value="1 ms" value_list="1 ms,,2 ms,,5 ms" label="PROCPWRGD and SYS_PWROK high to SUS_STAT# de-assertion (tPCH46)" help_text="This setting configures the minimum timing from CPUPWRGD assertion to SUS_STAT#.  For further details see Skylake H / LP Platform Controller Hub EDS." />
        </PchTimerConfiguration>
        <SmbusSmlinkConfiguration label="SMBus / SMLink Configuration">
            <SMBusAsdEnable value="No" value_list="No,,Yes" label="Intel(R) SMBus ASD Address Enabled" help_text="This setting enables / disables the Intel(R) SMBus Alert Sending Device.  For details see Skylake H / LP SPI Programming guide." />
            <SMBusAsdAddress value="0x00" label="Intel(R) SMBus ASD Address" help_text="This setting configures the Intel(R) SMBus Alert Sending Device Address.  For details see Skylake H / LP SPI Programming guide." />
            <SMBusI2cEnable value="No" value_list="No,,Yes" label="Intel(R) SMBus I2C Address Enabled" help_text="This setting enables / disables the Intel(R) SMBus I2C Address.  Note: This setting is only used for testing purposes.  The recommended setting is 'No'." />
            <SMBusI2cAddress value="0x00" label="Intel(R) SMBus I2C Address" help_text="This setting configures the Intel(R) SMBus I2C Address.  Note: This setting is only used for testing purposes.  The recommended setting is '0x00'." />
            <SMBusMctpEnable value="No" value_list="No,,Yes" label="Intel(R) SMBus MCTP Address Enabled" help_text="This setting enables / disables the Intel(R) SMBus MCTP Address.  Note: This setting is only used for testing purposes.  The recommended setting is 'No'." />
            <SMBusMctpAddress value="0x00" label="Intel(R) SMBus MCTP Address" help_text="This setting configures the Intel(R) SMBus MCTP Address.  Note: This setting is only used for testing purposes.  The default setting is '0x00'." />
            <SMBusAsfId value="0x00000000" label="Intel(R) SMBus Subsystem Vendor &amp; Device ID for ASF" help_text="This setting configures the Intel(R) SMBus Subsystem Vendor &amp; Device ID for ASF.  For details see Skylake H / LP SPI Programming guide." />
            <SMBusTcoSlaveSelect value="Intel(R) SMBus" value_list="Intel(R) SMBus,,SMLink 0" label="SMBus / SMLink TCO Slave Connection" help_text="This setting configures the TCO Slave connection to ether the Intel(R) SMBus or SMLink0.  For further details see Skylake H / LP Platform Controller Hub EDS." />
            <SLink0Enable value="Yes" value_list="No,,Yes" label="SMLink0 Enabled" help_text="This setting enables / disables SMLink0 interface.  For further details see Skylake H / LP Platform Controller Hub EDS.  Note: If using Intel(R) NFC this setting must be set to 'Yes'." />
            <SLink0freq value="1 MHz" value_list="100 KHz,,400 KHz,,1 MHz" label="SMLink0 Frequency" help_text="This setting determines the frequency at which the SMLink0 will operate.  Note: The recommended setting is '1 MHz'." />
            <SLink1Enable value="Yes" value_list="No,,Yes" label="SMLink1 Enabled" help_text="This setting enables / disables SMLink1 interface.  For further details see Skylake H / LP Platform Controller Hub EDS.  Note: This setting must be set to 'Yes' if using PCH / MCP Thermal reporting." />
            <SLink1freq value="100 KHz" value_list="100 KHz,,400 KHz,,1 MHz" label="SMLink1 Frequency" help_text="This setting determines the frequency at which the SMLink1 will operate.  Note: The recommended setting is '100KHz'." />
            <SLink1GPTargetAddress value="0x00" label="SMLink1 GP Target Address" help_text="This setting configures SMLink1 GP Target Address.  For further details see Skylake H / LP Platform Controller Hub EDS." />
            <SLink1GPTargetEnable value="No" value_list="No,,Yes" label="SMLink1 GP Target Address Enabled" help_text="This setting enables / disables SMLink1 GP Target Address interface.  For further details see Skylake H / LP Platform Controller Hub EDS.  Note: This setting must be set to 'Yes' if using PCH / MCP Thermal reporting." />
            <SLink1I2cAddress value="0x00" label="SMLink1 I2C Target Address" help_text="This setting configures SMLink1 I2C Target Address.  For further details see Skylake H / LP Platform Controller Hub EDS." />
            <SLink1I2cEnable value="No" value_list="No,,Yes" label="SMLink1 I2C Target Address Enabled" help_text="This setting enables / disables the SMLink1 I2C Target Address.  For further details see Skylake H / LP Platform Controller Hub EDS." />
        </SmbusSmlinkConfiguration>
    </InternalPchBuses>
    <Gpio label="GPIO">
        <MeFeaturePins label="ME Feature Pins">
            <NfcRst value="None" value_list="None,,GPP_A_0,,GPP_A_1,,GPP_A_2,,GPP_A_3,,GPP_A_4,,GPP_A_5,,GPP_A_6,,GPP_A_7,,GPP_A_8,,GPP_A_9,,GPP_A_10,,GPP_A_11,,GPP_A_13,,GPP_A_14,,GPP_A_15,,GPP_A_16,,GPP_B_0,,GPP_B_1,,GPP_B_2,,GPP_B_3,,GPP_B_4,,GPP_B_5,,GPP_B_6,,GPP_B_7,,GPP_B_8,,GPP_B_9,,GPP_B_10,,GPP_B_11,,GPP_B_12,,GPP_B_13,,GPP_B_14,,GPP_B_15,,GPP_B_16,,GPP_B_17,,GPP_B_18,,GPP_B_19,,GPP_B_20,,GPP_B_21,,GPP_B_22,,GPP_B_23,,GPP_C_0,,GPP_C_1,,GPP_C_2,,GPP_C_3,,GPP_C_4,,GPP_C_5,,GPP_C_6,,GPP_C_7,,GPP_C_8,,GPP_C_9,,GPP_C_10,,GPP_C_11,,GPP_C_12,,GPP_C_13,,GPP_C_14,,GPP_C_15,,GPP_C_16,,GPP_C_17,,GPP_C_18,,GPP_C_19,,GPP_C_20,,GPP_C_21,,GPP_C_22,,GPP_C_23,,GPP_D_4,,GPP_D_5,,GPP_D_6,,GPP_D_7,,GPP_D_8,,GPP_D_9,,GPP_D_10,,GPP_D_11,,GPP_D_12,,GPP_D_13,,GPP_D_14,,GPP_D_15,,GPP_D_16,,GPP_D_17,,GPP_D_18,,GPP_D_19,,GPP_D_20,,GPP_D_23,,GPP_E_0,,GPP_E_1,,GPP_E_2,,GPP_E_3,,GPP_E_4,,GPP_E_5,,GPP_E_6,,GPP_E_7,,GPP_E_8,,GPP_E_9,,GPP_E_10,,GPP_E_11,,GPP_E_12,,GPP_E_13,,GPP_E_14,,GPP_E_15,,GPP_E_16,,GPP_E_17,,GPP_E_18,,GPP_E_19,,GPP_E_20,,GPP_E_21,,GPP_E_22,,GPP_E_23,,GPP_F_0,,GPP_F_1,,GPP_F_2,,GPP_F_3,,GPP_F_4,,GPP_F_5,,GPP_F_6,,GPP_F_7,,GPP_F_8,,GPP_F_9,,GPP_F_10,,GPP_F_11,,GPP_F_12,,GPP_F_13,,GPP_F_14,,GPP_F_15,,GPP_F_16,,GPP_F_17,,GPP_F_18,,GPP_F_19,,GPP_F_20,,GPP_F_21,,GPP_F_22,,GPP_F_23,,GPP_G_0,,GPP_G_1,,GPP_G_2,,GPP_G_3,,GPP_G_4,,GPP_G_5,,GPP_G_6,,GPP_G_7,,GPD_0,,GPD_1,,GPD_2,,GPD_3,,GPD_4,,GPD_5,,GPD_6,,GPD_7,,GPD_8,,GPD_9,,GPD_10,,GPD_11" label="NFC Reset GPIO Select" help_text="NFC must be enabled in the Networking &amp; Connectivity section to configure this setting." />
            <NfcIrq value="None" value_list="None,,GPP_A_0,,GPP_A_1,,GPP_A_2,,GPP_A_3,,GPP_A_4,,GPP_A_5,,GPP_A_6,,GPP_A_7,,GPP_A_8,,GPP_A_9,,GPP_A_10,,GPP_A_11,,GPP_A_13,,GPP_A_14,,GPP_A_15,,GPP_A_16,,GPP_B_0,,GPP_B_1,,GPP_B_2,,GPP_B_3,,GPP_B_4,,GPP_B_5,,GPP_B_6,,GPP_B_7,,GPP_B_8,,GPP_B_9,,GPP_B_10,,GPP_B_11,,GPP_B_12,,GPP_B_13,,GPP_B_14,,GPP_B_15,,GPP_B_16,,GPP_B_17,,GPP_B_18,,GPP_B_19,,GPP_B_20,,GPP_B_21,,GPP_B_22,,GPP_B_23,,GPP_C_0,,GPP_C_1,,GPP_C_2,,GPP_C_3,,GPP_C_4,,GPP_C_5,,GPP_C_6,,GPP_C_7,,GPP_C_8,,GPP_C_9,,GPP_C_10,,GPP_C_11,,GPP_C_12,,GPP_C_13,,GPP_C_14,,GPP_C_15,,GPP_C_16,,GPP_C_17,,GPP_C_18,,GPP_C_19,,GPP_C_20,,GPP_C_21,,GPP_C_22,,GPP_C_23,,GPP_D_4,,GPP_D_5,,GPP_D_6,,GPP_D_7,,GPP_D_8,,GPP_D_9,,GPP_D_10,,GPP_D_11,,GPP_D_12,,GPP_D_13,,GPP_D_14,,GPP_D_15,,GPP_D_16,,GPP_D_17,,GPP_D_18,,GPP_D_19,,GPP_D_20,,GPP_D_23,,GPP_E_0,,GPP_E_1,,GPP_E_2,,GPP_E_3,,GPP_E_4,,GPP_E_5,,GPP_E_6,,GPP_E_7,,GPP_E_8,,GPP_E_9,,GPP_E_10,,GPP_E_11,,GPP_E_12,,GPP_E_13,,GPP_E_14,,GPP_E_15,,GPP_E_16,,GPP_E_17,,GPP_E_18,,GPP_E_19,,GPP_E_20,,GPP_E_21,,GPP_E_22,,GPP_E_23,,GPP_F_0,,GPP_F_1,,GPP_F_2,,GPP_F_3,,GPP_F_4,,GPP_F_5,,GPP_F_6,,GPP_F_7,,GPP_F_8,,GPP_F_9,,GPP_F_10,,GPP_F_11,,GPP_F_12,,GPP_F_13,,GPP_F_14,,GPP_F_15,,GPP_F_16,,GPP_F_17,,GPP_F_18,,GPP_F_19,,GPP_F_20,,GPP_F_21,,GPP_F_22,,GPP_F_23,,GPP_G_0,,GPP_G_1,,GPP_G_2,,GPP_G_3,,GPP_G_4,,GPP_G_5,,GPP_G_6,,GPP_G_7,,GPD_0,,GPD_1,,GPD_2,,GPD_3,,GPD_4,,GPD_5,,GPD_6,,GPD_7,,GPD_8,,GPD_9,,GPD_10,,GPD_11" label="NFC IRQ GPIO Select" help_text="NFC must be enabled in the Networking &amp; Connectivity section to configure this setting." />
            <FwUpdate value="None" value_list="None,,GPP_A_0,,GPP_A_1,,GPP_A_2,,GPP_A_3,,GPP_A_4,,GPP_A_5,,GPP_A_6,,GPP_A_7,,GPP_A_8,,GPP_A_9,,GPP_A_10,,GPP_A_11,,GPP_A_13,,GPP_A_14,,GPP_A_15,,GPP_A_16,,GPP_B_0,,GPP_B_1,,GPP_B_2,,GPP_B_3,,GPP_B_4,,GPP_B_5,,GPP_B_6,,GPP_B_7,,GPP_B_8,,GPP_B_9,,GPP_B_10,,GPP_B_11,,GPP_B_12,,GPP_B_13,,GPP_B_14,,GPP_B_15,,GPP_B_16,,GPP_B_17,,GPP_B_18,,GPP_B_19,,GPP_B_20,,GPP_B_21,,GPP_B_22,,GPP_B_23,,GPP_C_0,,GPP_C_1,,GPP_C_2,,GPP_C_3,,GPP_C_4,,GPP_C_5,,GPP_C_6,,GPP_C_7,,GPP_C_8,,GPP_C_9,,GPP_C_10,,GPP_C_11,,GPP_C_12,,GPP_C_13,,GPP_C_14,,GPP_C_15,,GPP_C_16,,GPP_C_17,,GPP_C_18,,GPP_C_19,,GPP_C_20,,GPP_C_21,,GPP_C_22,,GPP_C_23,,GPP_D_4,,GPP_D_5,,GPP_D_6,,GPP_D_7,,GPP_D_8,,GPP_D_9,,GPP_D_10,,GPP_D_11,,GPP_D_12,,GPP_D_13,,GPP_D_14,,GPP_D_15,,GPP_D_16,,GPP_D_17,,GPP_D_18,,GPP_D_19,,GPP_D_20,,GPP_D_23,,GPP_E_0,,GPP_E_1,,GPP_E_2,,GPP_E_3,,GPP_E_4,,GPP_E_5,,GPP_E_6,,GPP_E_7,,GPP_E_8,,GPP_E_9,,GPP_E_10,,GPP_E_11,,GPP_E_12,,GPP_E_13,,GPP_E_14,,GPP_E_15,,GPP_E_16,,GPP_E_17,,GPP_E_18,,GPP_E_19,,GPP_E_20,,GPP_E_21,,GPP_E_22,,GPP_E_23,,GPP_F_0,,GPP_F_1,,GPP_F_2,,GPP_F_3,,GPP_F_4,,GPP_F_5,,GPP_F_6,,GPP_F_7,,GPP_F_8,,GPP_F_9,,GPP_F_10,,GPP_F_11,,GPP_F_12,,GPP_F_13,,GPP_F_14,,GPP_F_15,,GPP_F_16,,GPP_F_17,,GPP_F_18,,GPP_F_19,,GPP_F_20,,GPP_F_21,,GPP_F_22,,GPP_F_23,,GPP_G_0,,GPP_G_1,,GPP_G_2,,GPP_G_3,,GPP_G_4,,GPP_G_5,,GPP_G_6,,GPP_G_7,,GPD_0,,GPD_1,,GPD_2,,GPD_3,,GPD_4,,GPD_5,,GPD_6,,GPD_7,,GPD_8,,GPD_9,,GPD_10,,GPD_11" label="NFC DFU GPIO Select" help_text="NFC must be enabled in the Networking &amp; Connectivity section to configure this setting." />
        </MeFeaturePins>
    </Gpio>
    <Power label="Power">
        <PlatformPower label="Platform Power">
            <SlpAGpd6Config value="SLP_A#" value_list="SLP_A#,,GPD6" label="SLP_A# / GPD6 Signal Configuration" help_text="This setting allows the user to assign the SLP_A# Power Control signal as SLP_A# or as GPD6.  For further details see Skylake H / LP Platform Controller Hub EDS." />
            <SlpS3Gpd4Config value="SLP_S3#" value_list="SLP_S3#,,GPD4" label="SLP_S3# / GPD4 Signal Configuration" help_text="This setting allows the user to assign the SLP_S3# Power Control signal as SLP_S3# or as GPD4.  For further details see Skylake H / LP Platform Controller Hub EDS." />
            <SlpS4Gpd5Config value="SLP_S4#" value_list="SLP_S4#,,GPD5" label="SLP_S4# / GPD5 Signal Configuration" help_text="This setting allows the user to assign the SLP_S4# Power Control signal as SLP_S4# or as GPD5.  For further details see Skylake H / LP Platform Controller Hub EDS." />
            <SlpS5Gpd10Config value="SLP_S5#" value_list="SLP_S5#,,GPD10" label="SLP_S5# / GPD10 Signal Configuration" help_text="This setting allows the user to assign the SLP_S5# Power Control signal as SLP_S5# or as GPD10.  For further details see Skylake H / LP Platform Controller Hub EDS." />
        </PlatformPower>
        <IntelMePowerConfiguration label="Intel(R) ME Power Configuration">
            <M3PowerRailConfig value="No" value_list="No,,Yes" label="M3 Power Rail Available" help_text="This setting enables / disables support for M3 operation of the firmware.  Note: Support for M3 is dependent on HW board design.  For Intel(R) vPro platform this setting must be set to 'Yes'." />
        </IntelMePowerConfiguration>
        <DeepSx label="Deep Sx">
            <DeepSxSupportEnable value="Yes" value_list="No,,Yes" label="Deep Sx Enabled" help_text="This setting enables / disables support for Deep Sx operation.  For further details see Skylake H / LP Platform Controller Hub EDS.  Note: Support for Deep Sx is board design dependent." />
        </DeepSx>
    </Power>
    <IntegratedSensorHub label="Integrated Sensor Hub">
        <IshSupported value="No" value_list="No,,Yes" label="Integrated Sensor Hub Supported" help_text="This setting allows customers to disable ISH on the platform." />
        <IshPowerUpState value="Disabled" value_list="Disabled,,Enabled" label="Integrated Sensor Hub Initial Power Up State" help_text="This setting allows customers to determine the power up state for ISH." />
        <IshSigningPolicy value="Intel" value_list="Intel,,OEM" label="Integrated Sensor Hub Signing Policy" help_text="This setting determines ISH signing will be checked against the Intel provisioned hash included in the base image or OEM public key hash provisioned on the platform." />
        <IshImage label="ISH Image">
            <Length value="0x40000" help_text="Total size (in bytes) of the ISH code partition including reserved space. It is recommended to be at least 256kb." />
            <InputFile value="" help_text="Path to your ISH firmware binary file." />
        </IshImage>
        <IshData label="ISH Data">
            <PdtBinary value="" label="PDT Binary File" help_text="Path to your PDT binary file" />
        </IshData>
    </IntegratedSensorHub>
    <Debug label="Debug">
        <IntelMeFirmwareDebuggingOverrides label="Intel(R) ME Firmware Debugging Overrides">
            <DbgOverridePreProdSi value="0x0" label="Debug Override Pre-Production Silicon" help_text="Allows the OEM to control FW features to assist with pre-production platform debugging.  This control has no effect if used on production silicon.  Note: Certain options will do not work when the descriptor is locked (See FW Bring-up Guide for setting details." />
            <DbgOverrideProdSi value="0x0" label="Debug Override Production Silicon" help_text="Allows the OEM to control FW features to assist with production platform debugging.  Note: Certain options will do not work when the descriptor is locked (See FW Bring-up Guide for setting details." />
            <MERstCapCLRst1Enabled value="No" value_list="No,,Yes" label="Enable Intel(R) ME Reset Capture on CLR_RST#" help_text="This setting configures Intel(R) ME behavior when it resets during CL_RST#1.  Note: The recommended default for this setting is 'No'." />
            <MERomBypassEnable value="No" value_list="No,,Yes" label="Firmware ROM Bypass" help_text="This setting enables / disables firmware ROM bypass.  Note: This setting only has affect when the firmware being used has ROM Bypass code present." />
        </IntelMeFirmwareDebuggingOverrides>
        <DirectConnectInterfaceConfiguration label="Direct Connect Interface Configuration">
            <DciEnable value="No" value_list="No,,Yes" label="Direct Connect Interface (DCI) Enabled" help_text="This setting enables / disables the DCI interface used for Intel(R) Trace Hub debugging." />
        </DirectConnectInterfaceConfiguration>
        <IntelTraceHubTechnology label="Intel(R) Trace Hub Technology">
            <RomTraceEmergencyModeEn value="No" value_list="No,,Yes" label="Intel(R) Trace Hub Emergency Mode Enabled" help_text="This setting enables / disables Intel(R) Trace Hub in the firmware base image." />
            <RomTraceSoftEnable value="No" value_list="No,,Yes" label="Intel(R) Trace Hub Soft Enable" help_text="This setting configures the Intel(R) Trace Hub soft enable.  Note: When enabling this setting you also need to enable the Intel(R) Trace Hub Debug Messages setting for proper operation." />
            <RomTraceDbgMsgsEnable value="No" value_list="No,,Yes" label="Intel(R) Trace Hub Debug Messages Enabled" help_text="This setting enables / disables the Intel(R) Trace Hub debug messages.  Note: When enabling this setting you must also enable the Intel(R) Trace Soft Enable setting for proper operation." />
            <UnlockToken value="" label="Unlock Token" help_text="This allows the OEM to input an Unlock Token binary file for closed chassis debug." />
            <UnlockTokenKeyHash value="00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00" label="Unlock Token Key Hash" help_text="This allows the OEM to input the hash of the public key needed to verify an OEM Unlock Token. The hash is SHA256 (32-bytes) but will be truncated to the lower 8-bytes." />
        </IntelTraceHubTechnology>
        <Idlm label="IDLM">
            <IdlmFile value="" label="IDLM Binary" help_text="This allows an IDLM binary to be merged into output image built by Intel (R) FIT." />
        </Idlm>
        <PchIoFeatureOverrides label="PCH I/O Feature Overrides">
            <SkycamEnable value="Yes" value_list="Yes,,No" label="SkyCam Enabled" help_text="This setting enables / disables the Skycam feature in Skylake-LP based platforms. Note: This setting is a debug override for the Skycam feature, the recommended method to disable this feature is through BIOS." />
        </PchIoFeatureOverrides>
    </Debug>
    <CpuStraps label="CPU Straps">
        <HyperThreadingDisable value="No" value_list="No,,Yes" label="Disable Hyperthreading" help_text="This setting controls enabling / disabling of Hyper threading.  Note: This strap is intended for debugging purposes only.  See BIOS Spec for more details on enabling / disabling Hyper threading." />
        <NumActiveCores value="All" value_list="All,,1,,2,,3,,4" label="Number of Active Cores" help_text="This setting controls the number of active processor cores.  Note: This strap is intended for debugging purposes only.  See BIOS Spec for more details on enabling / disabling processor cores." />
        <BistInit value="No" value_list="No,,Yes" label="BIST Initialization" help_text="This setting determines if BIST will be run at platform reset after BIOS requested actions.  Note: This strap is intended for debugging purposes only." />
        <FlexRatio value="0x0" label="Flex Ratio" help_text="This setting controls the maximum processor non-turbo ratio.  Note: This strap is intended for debugging purposes only.  See BIOS Spec for more details on maximum processor non-turbo ratio configuration." />
        <CpuMaxFreqBoot value="Yes" value_list="No,,Yes" label="Processor Boot Max Frequency" help_text="This setting determines if the processor will operate at maximum frequency at power-on and boot.  Note: This strap is intended for debugging purposes only." />
        <JtagPwrDisable value="No - No JTAG Power on C10 and Lower" value_list="No - No JTAG Power on C10 and Lower,,Yes - JTAG Power on C10 and Lower" label="JTAG Power Disable" help_text="This setting determines if JTAG power will be maintained on C10 or lower power states.  Note: This strap is intended for debugging purposes only." />
        <SaPowerPlaneTopology value="0x2" label="SA Power Plane Topology" help_text="This setting determines the SA power plane topology.  See Processor EDS for details.  Note: This strap should be left at the recommended default setting." />
        <SaVrType value="SVID" value_list="SVID,,Fixed VR" label="SA VR Type" help_text="This setting determines the SA core domain VR type.  See Processor EDS for details." />
        <IaPowerPlaneTopology value="0x0" label="IA Power Plane Topology" help_text="This setting determines the IA power plane topology.  See Processor EDS for details.  Note: This strap should be left at the recommended default setting." />
        <IaVrType value="SVID" value_list="SVID,,Fixed VR" label="IA Power Plane VR" help_text="This setting determines the IA core domain VR type.  See Processor EDS for details." />
        <RingPowerPlaneTopology value="0x0" label="Ring Power Plane Topology" help_text="This setting determines the Ring power plane topology.  See Processor EDS for details.  Note: This strap should be left at the recommended default setting." />
        <RingVrType value="SVID" value_list="SVID,,Fixed VR" label="Ring VR Type" help_text="This setting determines the Ring domain VR type.  See Processor EDS for details." />
        <GtUsPowerPlaneTopology value="0x1" label="GT_US Power Plane Topology" help_text="This setting determines the GT Unslice power plane topology.  See Processor EDS for details.  Note: This strap should be left at the recommended default setting." />
        <GtUsVrType value="SVID" value_list="SVID,,Fixed VR" label="GT_US VR Type" help_text="This setting determines the GT Unslice domain VR type.  See Processor EDS for details." />
        <GtSPowerPlaneTopology value="0x1" label="GT_S Power Plane Topology" help_text="This setting determines the GT slice power plane topology.  See Processor EDS for details.  Note: This strap should be left at the recommended default setting." />
        <GtSVrType value="SVID" value_list="SVID,,Fixed VR" label="GT_S VR Type" help_text="This setting determines the GT slice domain VR type.  See Processor EDS for details." />
        <SvidPresence value="SVID Present" value_list="SVID Present,,SVID Not Present" label="SVID Presence" help_text="This setting determine if SVID rails are present on the platform.  See Processor EDS for details." />
        <PlatformImonDisable value="0x0" label="Platform IMON Disable" help_text="This strap should be left at the recommended default setting." />
        <EopioPowerPlaneTopology value="0x0" label="eOPIO Power Plane Topology" help_text="This setting determines the eOPIO power plane topology.  See Processor EDS for details.  Note: This strap should be left at the recommended default setting." />
        <EopioVrType value="Fixed VR" value_list="SVID,,Fixed VR" label="eOPIO VR Type" help_text="This setting determines the eOPIO domain VR type.  See Processor EDS for details." />
        <EdramPowerPlaneTopology value="0x0" label="EDRAM Power Plane Topology" help_text="This setting determines the EDRAM power plane topology.  See Processor EDS for details.  Note: This strap should be left at the recommended default setting." />
        <EdramVrType value="Fixed VR" value_list="SVID,,Fixed VR" label="EDRAM VR Type" help_text="This setting determines the EDRAM domain VR type.  See Processor EDS for details." />
        <SeKeyMode value="0" value_list="0,,1" label="SE Key Mode" help_text="Note: This strap should be left at the recommended default setting." />
    </CpuStraps>
</FitData>
